Pulse width modulators (PWMs) are a key circuit block in building power switching regulators. Conventional, analog technology pulse width modulator circuits must be adjusted to compensate for process-voltage-temperature (PVT) variations, while digital pulse width modulators offer much higher circuit precision tolerating wide PVT ranges. In addition, digital designs allow easy implementation of many circuit control functions, and are thus likely to be standard in future single-chip switcher designs.
Digital pulse with modulation is basically a digital controller pulse width generator where the system clock determined the pulse width accuracy and resolution. Very high system clock frequencies, greater than 100 mega-Hertz (MHz) are normally required to yield fine resolution. For instance, a 1.25 MHz, 7-bit pulse width modulator—having an 800 nanosecond (ns) pulse period with 128 resolution steps—requires a clock frequency of 160 MHz (1.25 MHz×128). This makes the design expensive and unsuitable for high-efficiency, low-power applications. To lower the clock frequency, a common practice involves utilizing a multiphase clocking scheme. However, such complex clocking systems generally result in various logic-timing problems.
There is, therefore, a need in the art for an improved digital pulse width modulator having accuracy and resolution controlled by a low frequency, multiphase clock.